1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof and more particularly, to a semiconductor device with a Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET) a gate insulator of which includes a ferroelectric, and a fabrication method of the device.
2. Description of the Prior Art
A ferroelectric has a property or character that a dielectric polarization is generated by an applied external electric field and that the dielectric polarization remains even in the absence of the external electric field. The remaining dielectric polarization is termed a "remanent polarization".
Utilizing the "remanent polarization" enables the formation of a nonvolatile semiconductor memory device.
Specifically, in the case where a ferroelectric is used as part of a gate insulator of a MISFET, a gate voltage, which is applied across a gate electrode and a semiconductor substrate on which the MISFET is formed, causes a dielectric polarization in the ferroelectric. The dielectric polarization thus caused remains even after the application of the gate voltage is stopped. In other words, a "remanent polarization" is generated in the ferroelectric after stopping the application of the gate voltage.
The remanent polarization induces electric charges in the opposing surface region of the substrate to the ferroelectric (i.e., a channel region of the MISFET). This means that the MISFET is kept in the ON state by the remanent polarization even in the absence of the gate voltage.
To turn the MISFET off, a reverse gate voltage is applied across the gate electrode and the substrate to remove the remanent polarization in the ferroelectric.
Thus, the MISFET including the ferroelectric in the gate insulator is capable of a nonvolatile memory function.
A conventional semiconductor device of this sort is shown in FIGS. 1 and 2, which was disclosed in the Japanese Non-Examined Patent Publication No. 2-90571 published in March 1990.
The conventional semiconductor device of FIGS. 1 and 2 is fabricated through the following process steps.
First, an isolation oxide layer 127 is selectively formed on a p-type silicon substrate 126, defining a plurality of device regions on the substrate 126. The substrate 126 is exposed from the isolation oxide layer 127 in the device regions.
In FIGS. 1 and 2, however, only one of the device regions is shown for the sake of simplification of description.
Next, a bismuth titanate (Bi.sub.4 Ti.sub.3 O.sub.12) layer 128 as a ferroelectric layer is formed on the field oxide layer 127 and the exposed substrate 126 over the whole substrate 126 by a RF sputtering process. Then, the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 is selectively etched by a reactive ion etching process using a patterned resist mask (not shown), thereby leaving selectively the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 with a rectangular plan shape on the exposed substrate 126. The remaining Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 is located on an area corresponding to the central part of a gate insulator 131, which is apart from the isolation oxide layer 127.
Further, the substrate 126 with the remaining Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 in the device region is subjected to a thermal oxidation process to form a silicon dioxide (SiO.sub.2) layer 129 on the exposed substrate 126 in the device region. The SiO.sub.2 layer 129 surrounds the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 in the device region. In other words, the SiO.sub.2 layer 129 covers the device region except for the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128.
Subsequently, a polysilicon layer (not shown) is formed on the SiO.sub.2 layer 129 and the isolation oxide layer 127 by a popular process, and is patterned to form a gate electrode 130 with a rectangular plan shape. The gate electrode 130 is placed on the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 and two parts 129a and 129b of the SiO.sub.2 layer 129 that are located at each side of the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128. The Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 and the parts 129a and 129b of the SiO.sub.2 layer 129 constitute a gate insulator 131. The remaining part 129c of the SiO.sub.2 layer 129, which is exposed from the gate electrode 130, covers the substrate 126 or device region.
Following this, using the polysilicon gale electrode 130 as a mask, arsenic (As) ions are selectively implanted into the substrate 126 in self-alignment with the gate electrode 130 and the isolation oxide layer 127 through the part 129c of the SiO.sub.2 layer 129. As a result, a source region 105 and a drain region 106 are formed in the device region at each side of the gate electrode 130.
The source and drain regions 105 and 106, the gate insulator 131, and the gate electrode 130 constitute a MISFET.
Thus, the conventional semiconductor device of FIGS. 1 and 2 is finished.
In the conventional semiconductor device of FIGS. 1 and 2, the gate insulator 131 of the MISFET is formed by the central part 128 made of Bi.sub.4 Ti.sub.3 O.sub.12 (which is a ferroelectric) and the remaining side parts 129a and 129b made of SiO.sub.2 (which is a dielectric).
The conventional semiconductor device of FIGS. 1 and 2 operates in the following way.
When a signal voltage is applied to the gate electrode 130, a dielectric polarization occurs in the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 and the parts 129a and 129b of the SiO.sub.2 layer 129 according to the polarity of the signal voltage. The dielectric polarization induces electric charges serving as a conductive channel at the corresponding surface area of the substrate 126 to the gate insulator 131.
The electric charges (i.e., the conductive channel) thus generated allow a drain current to flow between the source and drain regions 105 and 106, which means that the MISFET is in the ON state.
When the application of the signal voltage is stopped, the dielectric polarization disappears in the parts 129a and 129b of the SiO.sub.2 layer 129. Therefore, the electric charges generated below the parts 129a and 129b disappear. However, a remanent polarization remains in the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 even in the absence of the gate voltage. Consequently, a large part of the electric charges induced below the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 are left, thereby keeping the MISFET in the ON state.
With the conventional semiconductor device of FIGS. 1 and 2, there is an advantage that the level of an output signal is able to be controlled by changing the rate or percentage of the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 with respect to the whole gate insulator 131. In other words, logic circuits providing a multilevel output in response to a two-valued input (i.e., "0" and "1") are able to be designed.
Another conventional semiconductor device of this sort is shown in FIG. 3, which was disclosed in the Japanese Non-Examined Patent Publication No. 6-29549 published in February 1994.
In the conventional semiconductor device of FIG. 3, an n-type source region 205 and an n-type drain region 206 are formed to be apart from each other in a p-type silicon substrate 226. A gate insulator 231 with a two-layer structure is formed on the substrate 226 so as to link the source and drain regions 205 and 206 with each other.
The gate insulator 131 is formed by a SiO.sub.2 layer 211 located in a lower level and a lead zirconate titanate (Pb(Zr--Ti)O.sub.3, PZT) layer 222 located in an upper level. Unlike the conventional semiconductor device of FIGS. 1 and 2, the PZT layer 222 is not contacted with the substrate 226. The SiO.sub.2 layer 211 is contacted with the substrate 226.
A gate electrode 204 is formed on the gate insulator 231. The gate electrode 204 is contacted with the PZT layer 222 in the upper level.
The source and drain regions 205 and 206, the gate insulator 231, and the gate electrode 204 constitute a MISFET.
To adjust the threshold voltage of the MISFET, an ion-implanted region 232 is formed in the surface region of the substrate 226 between the source and drain regions 205 and 206.
With the conventional semiconductor device of FIG. 3, since the gate insulator 231 is formed by the lower layer 211 of a dielectric (i.e., SiO.sub.2) and the upper layer 222 of a ferroelectric (i.e., PZT), the substrate 226 is not contacted with the PZT layer 22. Therefore, there is an advantage that the degree of freedom increases in material selection for the gate insulator 231 to thereby improve the surface state of a channel region (i.e., the substrate 226) between the source and drain regions 205 and 206.
Still another conventional semiconductor device of this sort is shown in FIG. 4, which was disclosed in the Japanese Non-Examined Patent Publication No. 5-145077 published in June 1993.
In the conventional semiconductor device of FIG. 4, a p-type well 333 is formed in a silicon substrate (not shown). An n.sup.+ -type source region 305 and an n.sup.+ -type drain region 306 are formed to be apart from each other in the p-type well 333. A gate insulator 339 with a three-layer structure is formed on the well 333 to link the source and drain regions 305 and 306 with each other.
The gate insulator 339 includes a dielectric layer 334 made of strontium titanate (SrTiO.sub.3) with a high dielectric constant, a conductive layer 335 made of platinum (Pt), and a ferroelectric layer 336 made of lead titanate (PbTiO.sub.3, PT). Like the conventional semiconductor device of FIG. 3, the PT layer 336 is not contacted with the well 333 (i.e. the substrate). The SrTiO.sub.3 layer 334 is contacted with the well 333.
A gate electrode 337 is formed on the gate insulator 339. A channel region 338 is formed below the gate insulator 339 between the source and drain regions 305 and 306.
With the conventional semiconductor device of FIG. 4, since the gate insulator 339 is formed by the lower layer 334 of a dielectric (i.e., SrTiO.sub.3), the middle layer 335 of a conductor (i.e., Pt), and the upper layer 336 of a ferroelectric (i.e., PT), the well 333 or substrate is not contacted with the PT layer 336. Therefore, there is the same advantage as that of the conventional device of FIG. 3.
However, the above-described three conventional semiconductor devices have the following problems.
With the conventional semiconductor device of FIGS. 1 and 2, because the SiO.sub.2 layer 129 is formed by the thermal oxidation process, the opposing ends of the layer 129 to the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 are located beneath the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128, as clearly shown in FIG. 2. In other words, the periphery of the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 is overlapped with the inner ends of the parts 129a and 129b of the SiO.sub.2 layer 129 at corresponding areas 139, respectively.
As a result, an obtainable drain current by the remanent polarization in the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 decreases, the reason of which is as follows.
After selectively forming the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 on the exposed surface of the substrate 126, the SiO.sub.2 layer 129 is formed by the thermal oxidation process. During this oxidation process, SiO.sub.2 grows not only vertically but also laterally due to oxidation of the surface area of the silicon substrate 126, resulting in the inner ends of the SiO.sub.2 layer 129 located under the periphery of the remaining Bi.sub.4 Ti.sub.3 O.sub.12 layer 128.
The width of the overlapping areas 139 is typically equal to approximately 20% of the thickness of the SiO.sub.2 layer 129. Therefore, the total width of the overlapping areas 139 is equal to approximately 40% of the thickness of the SiO.sub.2 layer 129.
In the overlapping areas 139, when a gate voltage is applied across the gate electrode 130 and the substrate 126, the voltage is divided into two by the overlapped layers 129 and 128. This means that the effective voltage applied across the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 decreases in the overlapping areas 139.
Consequently, the obtainable strength of the dielectric polarization (and therefore, remanent polarization) in the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 is reduced. This means that the obtainable value of a drain current by the remanent polarization decreases compared with the case where the overlapping areas 139 do not exist.
Supposing that the whole remanent polarization of the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 in the overlapping areas 139 becomes ineffective, the obtainable value of the drain current will decrease by approximately 40% of the value in the case where no overlapping areas exist. For example, if the SiO.sub.2 layer 129 has a thickness of 20 nm, the width of the overlapping areas 139 is approximately 8 nm. If the width of the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 is 0.8 m, the value of 8 nm is equal to 1% of the width of the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128. Thus, the drain current will decrease by 1%.
This drain current decrease will become more and more with the progressing device miniaturization.
With the conventional semiconductor device of FIGS. 1 and 2, narrowing the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 makes it possible to decrease the level of a drain current at the time no signal voltage is applied to the gate electrode 130. However, the rate or percentage of the overlapping areas 139 will relatively increase with the progressing device miniaturization and therefore, the obtainable value of a drain current will decrease further.
Consequently, the effect by the overlapping areas 139 to the relationship between the size of the Bi.sub.3 Ti.sub.3 O.sub.12 layer 128 and the obtainable value of a drain current will not become negligible.
The shape and structure of the overlapping areas 139 are complicated and the characteristic of the Bi.sub.4 Ti.sub.3 O.sub.12 layer 128 is varied or fluctuated according to the magnitude of the applied signal voltage. Accordingly, it is very difficult to estimate in advance the effect of the overlapping areas 139 by calculation.
To correct various errors caused by the overlapping areas 139, a lot of study is essential for the purpose of measuring the relationship between a drain current and the device size. This increases the difficulty in designing the semiconductor devices of this sort.
With the conventional semiconductor device of FIG. 3, the lower SiO.sub.2 layer 211 is formed on the substrate 226 to be contacted therewith, and the upper PZT layer 222 is formed on the SiO.sub.2 layer 211. Therefore, the peripheral area of the PZT layer 222 tends to be readily oxidized due to the existence of the SiO.sub.2 layer 211.
The oxidation of the PZT layer 222 highly affects the relationship between the size of the PZT layer 222 and the obtainable value of a drain current. As a result, the difficulty in device design is further increased.
With the conventional semiconductor device of FIG. 4, the SrTiO.sub.3 layer 334 is formed on the well (i.e., the substrate) 333, and the PT layer 336 is formed over the SrTiiO.sub.3 layer 334 through the Pt layer 335. Therefore, the PT layer 336 tends to be readily oxidized in the peripheral area of the layer 336.
Thus, there arises the same problem as that of the semiconductor device of FIG. 3.